The present invention relates to a magnetoresistive random access memory (MRAM), in particular to an MRAM in which data is written using domain wall displacement.
The MRAM is a storage device which uses a magnetic body as a storage element and stores information corresponding to a magnetization direction of the magnetic body. The MRAM is expected as a high-speed and infinitely-rewritable non-volatile memory and is being actively developed.
There are various types of MRAMs and one of them is a so-called domain wall displacement type MRAM. In the domain wall displacement type MRAM, a spin-polarized current is passed through a ferromagnetic layer that stores data (hereinafter may be referred to as “magnetic recording layer” in the present specification) in a direction corresponding to the data and the position of the domain wall is displaced, so that the data is written. For example, the domain wall displacement type MRAM is disclosed in international publications WO2006/115275, WO2009/037910, WO2009/038004, and WO2009/001706 and “Low-Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM”, 2009 Symposium on VLSI Circuits, 12A-2, pp. 230-231. Here, WO2006/115275, WO2009/037910, and WO2009/038004 discloses an MRAM using a magnetic recording layer in which the magnetization direction is in an in-plane direction and WO2009/001706 discloses an MRAM using a magnetic recording layer in which the magnetization direction is in a film thickness direction.
FIG. 1 is a perspective view showing a schematic configuration of a memory cell of one bit of the domain wall displacement type MRAM disclosed in WO2009/001706. The memory cell shown in FIG. 1 includes one MRAM element 101 and two nMOS transistors 102-1 and 102-2. The gates of the nMOS transistors 102-1 and 102-2 are coupled to a word line 111. The MRAM element 101 includes magnetization fixed layers 103-1 and 103-2, a magnetic recording layer 104 formed to bridge the two magnetization fixed layers 103-1 and 103-2, a spacer layer 105 of a thin insulator provided to be in contact with the approximate center of the magnetic recording layer 104, and a reference layer 106 provided over the spacer layer 105.
The magnetization fixed layers 103-1 and 103-2 are ferromagnetic layers having fixed magnetization directions opposite to each other, respectively. In the memory cell shown in FIG. 1, the magnetization direction of the magnetization fixed layer 103-1 is upward and the magnetization direction of the magnetization fixed layer 103-2 is downward. The magnetization fixed layers 103-1 and 103-2 are coupled to write bit lines 112-1 and 112-2 through the nMOS transistors 102-1 and 102-2, respectively.
The magnetic recording layer 104 is a ferromagnetic layer used to store data. The magnetization directions of magnetization fixed domains 107-1 and 107-2 in the magnetic recording layer 104, which are in contact with the magnetization fixed layers 103-1 and 103-2, are fixed to the same directions as those of the magnetization fixed layers 103-1 and 103-2, respectively. The magnetization direction of a magnetization reversal domain 108 between the magnetization fixed domains 107-1 and 107-2 can be reversed in the vertical direction. Data is stored by assigning the magnetization directions of the magnetization reversal domain 108 to data “0” and data “1” respectively. A domain wall with which domains magnetized in opposite directions are in contact is formed on a boundary between the magnetization fixed domain 107-1 and the magnetization reversal domain 108 or on a boundary between the magnetization fixed domain 107-2 and the magnetization reversal domain 108. As described later, in the memory cell shown in FIG. 1, data is written by moving the domain wall by the spin-polarized current.
The reference layer 106 is a magnetic layer having a fixed magnetization direction. In the memory cell shown in FIG. 1, the magnetization direction of the reference layer 106 is fixed upward. For example, the reference layer 106 is formed of SAF (synthetic antiferromagnet) which is formed as a laminated structure of a non-magnetic body and a ferromagnetic body and to which diamagnetism is artificially given. The reference layer 106 is coupled to a read bit line 113.
Data is written by reversing the magnetization direction of the magnetization reversal domain 108 of the magnetic recording layer 104 by moving the domain wall by passing a write current through the magnetization reversal domain 108. When a high potential is applied to the write bit line 112-1, a low potential is applied to the write bit line 112-2, and further a high potential is applied to the word line 111 to turn on both the nMOS transistors 102-1 and 102-2, the write current flows from the write bit line 112-1 to the write bit line 112-2 through the nMOS transistor 102-1, the magnetization fixed layer 103-1, the magnetic recording layer 104, the magnetization fixed layer 103-2, and the nMOS transistor 102-2. Thereby, a flow of electrons whose spins are aligned flows in a direction opposite to the direction of the write current, that is, in a direction from the magnetization fixed domain 107-2 to the magnetization fixed domain 107-1 and the domain wall formed in the magnetic recording layer 104 moves to the side of the magnetization fixed domain 107-1, so that the magnetization direction of the magnetization reversal domain 108 becomes the same as that of the magnetization fixed domain 107-2. On the other hand, when a high potential is applied to the write bit line 112-2, a low potential is applied to the write bit line 112-1, and a high potential is applied to the word line 111 to turn on the nMOS transistors 102-1 and 102-2, the write current flows in the opposite direction, so that the magnetic recording layer 104 moves to the side of the magnetization fixed domain 107-2, so that the magnetization direction of the magnetization reversal domain 108 becomes the same as that of the magnetization fixed domain 107-1. Thereby, data “0” and data “1” can be written. The state of the magnetic recording layer 104 is not changed even when the power is turned off, so that the data is recorded in the magnetic recording layer 104 in a nonvolatile manner.
Data is read by detecting a change of a resistance value of the spacer layer 105 between the magnetic recording layer 104 and the reference layer 106. The reference layer 106 is magnetized in one direction. When the magnetization direction of the magnetization reversal domain 108 located below the reference layer 106 with the spacer layer 105 in between is that same as that of the reference layer 106, the resistance value of the spacer layer 105 decreases and when the magnetization direction is opposite to that of the reference layer 106, the resistance value increases. The resistance value is detected by flowing a read current between the read bit line 113 and the write bit lines 112-1 and 112-2.
FIG. 2 shows a diagram of a layout of the memory cell in FIG. 1. The word line 111 is formed of a polysilicon gate. The nMOS transistor 102-1 is made up of the word line 111 and a diffusion layer 121-1. The nMOS transistor 102-2 is made up of the word line 111 and a diffusion layer 121-2. The sources of the nMOS transistors 102-1 and 102-2 are coupled to the write bit lines 112-1 and 112-2 through vias 122-1 and 122-2, respectively. Here, both the write bit lines 112-1 and 112-2 are formed as metal wiring. Further, the drains of the nMOS transistors 102-1 and 102-2 are coupled to the magnetization fixed layers 103-1 and 103-2 through vias 123-1 and 123-2, respectively. Further, the reference layer 106 is coupled to the read bit line 113 through a via 124. The read bit line 113 is formed as metal wiring.
The memory cell shown in FIGS. 1 and 2 includes two transistors and further three metal wirings in a direction perpendicular to the word line 111, so that the size of the memory cell is constrained. The area of the memory cell shown in FIGS. 1 and 2 has to be larger than that of a memory cell of a DRAM (dynamic random access memory) and a flash memory, which includes only one transistor.